1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly, to a semiconductor memory device having a normal operation mode and a self-refresh mode.
2. Description of the Background Art
In recent years, portable computers have continued to be developed. A semiconductor memory device used in such a portable computer is required to have the capabilities of holding data such as file data which used to be performed by a conventional hard disk, and of operating with low power consumption in the data holding state.
In a semiconductor memory device, a self-refresh state generally corresponds to the data holding state.
Meanwhile, a technique to lower an external power supply voltage EXt.VCC in the data holding state (self-refresh mode), as shown in FIG. 27A, from about 3.3V in a write mode and a read mode to about 2.5V, for example, has been developed in order to reduce power consumption by portable computers. Herein, as shown in FIGS. 27B and 27C, switching from the write mode to the self-refresh mode is achieved by the generation of CBR (CAS Before RAS) timing in which an external column address strobe signal Ext./CAS is activated prior to an activation of an external row address strobe signal Ext./RAS. A self-refresh entry control signal /BBU is activated to a low (L:logical low) level as shown in FIG. 27D.
Reduction in an internal power supply voltage VCC in the data-holding state for power saving, however, causes the increase in a current Icc consumed in a substrate voltage generation circuit when voltage VCC is equal to or less than a voltage Vcl as shown by the solid line in FIG. 10. As a result, power consumption increases in the substrate voltage generation circuit, for example.
In addition, stable reading/writing operation from/to a memory cell is made difficult by lowering internal power-supply voltage VCC.
An object of the invention is, therefore, to provide a semiconductor memory device capable of stable operation with reduced power consumption in the data holding state (the self refresh-mode).
In accordance with one aspect of the invention, a semiconductor memory device includes a substrate, a memory cell array formed on the substrate and having a plurality of memory cells storing data, a memory cell selection circuit, formed on the substrate for selecting at least one of the plurality of memory cells from/to which data is read out/written, and, a substrate voltage generation circuit formed on the substrate for generating and supplying to the substrate a first substrate voltage when an internal power supply voltage is larger than a predetermined value and a second substrate voltage with an absolute value smaller than the absolute value of the first substrate voltage when the internal power supply voltage is smaller than the predetermined value.
In accordance with another aspect of the invention, a semiconductor memory device, having a normal operation mode and a self-refresh mode, includes a plurality of word lines, a plurality of bit line pairs orthogonal to the plurality of word lines, a plurality of memory cells arranged corresponding to crossings of the plurality of word lines and the plurality of bit line pairs, a bit line precharge circuit for supplying a bit line equivalent voltage to each one of the plurality of bit line pairs, a bit line equivalent voltage generation circuit for generating a bit line equivalent voltage, and a mode switching circuit for switching the mode between the normal operation mode and the self-refresh mode according to external control signals, and the bit line equivalent voltage generation circuit includes a resistive divider for dividing the internal power-supply voltage in two by resistance to generate the bit line equivalent voltage in the self-refresh mode.
In accordance with still another aspect of the invention, a semiconductor memory device, having a normal operation mode and a self-refresh mode, includes a plurality of word lines, a plurality of bit lines orthogonal to the plurality of word lines, a plurality of memory cells arranged corresponding to crossings of the plurality of word lines and the plurality of bit lines, a mode switching circuit for switching the mode between the normal operation mode and the self-refresh mode according to external control signals, and a word line selection circuit for simultaneously selecting less word lines of the plurality of word lines than are simultaneously selected in the normal operation mode, when the mode switching circuit switches the mode to the self-refresh mode.
Accordingly, an advantage of the invention lies in that the power consumption is surely reduced in the data holding state.
A further advantage of the invention is that increased stability can be obtained together with the reduction in power consumption in the self-refresh operation.
A still further advantage of the invention is that further reduction in power consumption can be obtained in the self-refresh mode.